The present invention relates generally to packages for integrated circuits (ICs). More specifically, the present invention relates to systems for and methods of testing grid array (GA) integrated circuit packages including column grid array packages (CGA).
Integrated circuits or ICs can be housed in an integrated circuit package. Generally, the integrated circuit or chip is mechanically and electrically attached to a substrate, such as, a ceramic or plastic substrate, and covered by a cap or plastic to protect the chip from environmental conditions. The package is attached to a printed wire board (PWB) or printed circuit board for use in an electrical device. The printed circuit board can be part of a card, a mother board, or another component of an electrical device.
Pins, columns or solder spheres are typically utilized between the substrate and the printed circuit board to provide a mechanical and electrical connection between the integrated circuit package and the printed circuit board. The top surface of the package substrate includes numerous metal contact pads which are electrically coupled through the substrate to the pins or solder spheres on the bottom surface of the package substrate. The packages associated with integrated circuits exist in a variety of forms including plastic ball grid array (PBGA) packages, ceramic ball grid array (CBGA) packages, ceramic column grid array (CCGA) packages, and tape bonded ball grid array (TBGA) packages.
Ceramic column grid array (CCGA) packages are utilized in applications which require high power dissipation. For example, CCGA packages generally have a higher power dissipation capability than PBGA or CBGA packages. The CCGA package utilizes solder columns instead of solder spheres associated with CBGA and PBGA packages. The solder columns connect the package substrate to the printed circuit board.
The solder columns of the CBGA packages provide better thermal strain relief than solder balls. The solder columns can be 10 tin (Sn)/90 lead (Pb) materials measuring 0.5 millimeters (mm) in diameter and 1.27 mm or 2.2 mm in height. Other configurations for the solder columns are possible.
Generally, solder columns for CCGA packages can be fabricated in two configurations. First, CCGA solder columns can be implemented as wire columns which are eutectic soldered to both the bottom side of the substrate and to the printed circuit board site. Second, CCGA solder columns can be cast columns which are high-temperature soldered to the substrate and eutectic soldered to the printed circuit board. Other techniques are possible for attaching the solder columns to the substrate and printed circuit board.
Generally, as integrated circuits and integrated circuit packages become smaller and the functionality of integrated circuits and integrated circuit packages increases, the density of connections between the printed circuit board and the integrated circuit package has increased. For example, current microprocessors require a relatively high density of pins, columns or solder balls. Current microprocessors are often provided in a ceramic leadless grid array (CLGA) package similar to a PGA package except that pins are replaced with pads. However, the thermal stress between the CLGA package and the PC board can cause reliability problems. Accordingly, a CCGA interposer with columns can be added between the CLGA package and the PC board to reduce thermal stress, thereby greatly improving the reliability of the CLGA PC board connection.
In the process of attaching the columns associated with the CCGA interposer or CCGA package, neighboring columns can be unintentionally shorted due to solder overflow. Various conventional test equipment can be utilized to determine if columns are shorted. For example, an X-ray real-time microscope can determine short circuits or short failures associated with the columns. In addition, a multi-curve tracer (e.g., manufactured by Ultra Test International, San Jose, Calif. can also be applied to locate short-circuited columns or failed sites. However, both of these conventional techniques require expensive equipment and are time consuming.
According to another technique, a conventional joint action test group (JTAG) tester for CLGA packages can be utilized. However, conventional JTAG testers are extremely expensive.
Thus, there is a need for a convenient and effective method of and apparatus for determining whether conductors of an IC package or interposer are short circuited. Further still, there is a need for a fast process for determining whether columns of a CCGA package or interposer are short circuited. Even further still, there is a need for a simple system and process that can determine the integrity of neighboring conductors of an IC package.
An exemplary embodiment relates to a test system for testing conductors of an integrated circuit package. The test system is capable of determining an existence of one or more short circuits between adjacent conductors. The system includes an interface and a control circuit. The interface is configured to electrically connect to the conductors of the integrated circuit package. The interface groups the conductors into a plurality of nodes. The number of nodes are no more than one-half the number of conductors. The control circuit is coupled to the interface and determines the existence of one or more short circuits between adjacent conductors in response to signals on the nodes.
Another exemplary embodiment relates to a method of testing conductors of an integrated circuit package. The conductors are tested to determine an existence of one or more short circuits between adjacent conductors. The method includes electrically coupling the conductors to an interface. The interface electrically connects to the conductors of the integrated circuit package and groups the conductors into a plurality of nodes. The number of nodes are no more than one-half the number of conductors. The method also includes providing signals to the nodes and comparing the signals at the nodes to determine the existence of one or more short circuits between adjacent conductors.
Still another embodiment relates to a test system for a column grid array (CGA) package or CGA interposer. The test system includes an interface means and a control means. The interface means receives columns of the column grid array package and groups the columns into eight or less nodes. The control means senses an existence of a short circuit between adjacent columns in response to signals from the nodes.